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[Other resource] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2015 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] ata.tar

Description: 硬盘接口的硬件实现，VHDL和Verilog是吸纳的，带有文档！-Hard disk interface hardware implementation, VHDL and Verilog is absorbed with documentation!
Platform: | Size: 832512 | Author: 刘志刚 | Hits:

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